In the DDL synchronous DRAM, a DLL (Delay Locked Loop) circuit is used to synchronize data input-and-output timings with an external clock signal. In many cases, the DLL circuit is provided with a duty detection circuit so that a duty of the internal clock signal becomes 50% (see Japanese Patent Application Laid-open No. 2006-303553).
FIG. 9 is a circuit diagram of a conventional duty detection circuit.
The duty detection circuit shown in FIG. 9 includes a detection line LDUTYHB connected to a contact node between a discharge transistor TR1 and a charge transistor TR3, a detection line LDUTYLB connected to a contact node between a discharge transistor TR2 and a charge transistor TR4, and a comparator circuit COMP that detects a potential difference of these detection lines LDUTYHB and LDUTYLB. Capacitances C1 and C2 are connected to the detection line LDUTYHB, and capacitances C3 and C4 are connected to the detection line LDUTYLB.
The discharge transistor TR1 and the charge transistor TR3 are controlled by gate circuits G1 and G3, respectively, and are brought into on state in response to an internal clock signal LCLKOET and a selection signal LDCSMT, respectively. On the other hand, the discharge transistor TR2 and the charge transistor TR4 are controlled by gate circuits G2 and G4, respectively, and are brought into on state in response to an internal clock signal LCLKOEB and a selection signal LDCSMB, respectively. The internal clock signal LCLKOET and the internal clock signal LCLKOEB are internal clock signals for duty detection, and are mutually complementary signals.
Sources of the discharge transistors TR1 and TR2 are connected in common to a discharge node BIASND. The discharge node BIASND is connected to a ground potential via a bias transistor N1. On the other hand, a precharge circuit P0 operating based on a precharge signal PRE is connected to the charge transistors TR3 and TR4.
FIG. 10 is an operation waveform diagram of the duty detection circuit shown in FIG. 9.
As shown in FIG. 10, the selection signal LDCSMT is activated during a period of a clock edge 0 to a clock edge 4, and the selection signal LDCSMB is activated during a period of a clock edge 1 to a clock edge 5. That is, these selection signals are activated with a half cycle deviation of the internal clock signal.
Based on the above, the detection line LDUTYHB is discharged when the internal clock signal LCLKOET becomes at a high level and is charged when the internal clock signal LCLKOET becomes at a low level, during a period while the selection signal LDCSMT is activated. Similarly, the detection line LDUTYLB is discharged when the internal clock signal LCLKOEB becomes at a high level and is charged when the internal clock signal LCLKOEB becomes at a low level, during a period while the selection signal LDCSMB is activated.
As a result, when the duty of the internal clock signal LCLKOET is large, the potential of the detection line LDUTYHB becomes low, and the potential of the detection line LDUTYLB becomes high. On the other hand, when the duty of the internal clock signal LCLKOET is small, the potential of the detection line LDUTYHB becomes high, and the potential of the detection line LDUTYLB becomes low. The comparator circuit COMP detects a potential difference ΔV obtained in this way, and generates a duty detection signal LUPDCT.
However, the conventional duty detection circuit shown in FIG. 9 has a problem in that discharge speeds of the discharge transistors TR1 and TR2 are different at the detection starting time. That is, while the discharge transistor TR1 is turned on at the clock edge 0, both the discharge transistors TR1 and TR2 are off during a preceding period. Therefore, a discharge node BIASND at the detection starting time is substantially at a ground potential. On the other hand, because the discharge transistor TR2 is turned on at the clock edge 1, the discharge node BIASND already increases at the detection starting time. Consequently, a difference occurs between the discharge speeds of the discharge transistors TR1 and TR2, and an accurate detection of duty cannot be performed.
Further, the conventional duty detection circuit shown in FIG. 9 has continuous two cycles as a detection period. Therefore, only an average value of the duty in an even cycle and the duty in an odd cycle can be obtained. For example, when the duty in the even cycle is 60% and when the duty of the odd cycle is 40%, the average value becomes 50%. As a result, duty correction is not performed.
When a so-called “two-phase DLL circuit” is used, the duty in the even cycle is different from the duty in the odd cycle. The two-phase DLL is a system that generates two frequency-divided signals by dividing an external clock signal into two, and generates an internal clock signal by combining the two frequency-divided signals after adjusting a delay amount of the frequency-divided signals. This type of DLL circuit is often used when the frequency of the external clock signal is high.
However, according to the two-phase DLL circuit, because the control of the internal clock signal in the even cycle is independent of the control of the internal clock signal in the odd cycle, the duty in the even cycle does not coincide with the duty in the odd cycle is some cases. In this case, the duty detection circuit shown in FIG. 9 cannot perform accurate detection.
As a method of solving the above problems, the present inventors have proposed an improved duty detection circuit in the past (see Japanese Patent Application Laid-open No. 2007-121114).
FIG. 11 is a circuit diagram of the improved duty detection circuit.
The duty detection circuit shown in FIG. 11 additionally includes a delay circuit D1 that delays the output of the gate circuit G2 while deleting the charge transistors TR3 and TR4 and the gate circuits G3 and G4 that control these charge transistors, in the duty detection circuit shown in FIG. 9.
FIG. 12 is an operation waveform diagram of the duty detection circuit shown in FIG. 11.
As shown in FIG. 12, in the present example, the selection signal LDCSMT is activated by dividing the period into a period of the clock edges 0 to 2 and a period of the clock edges 4 to 6, and the selection signal LDCSMB is activated by dividing the period into a period of the clock edges 1 to 3 and a period of the clock edges 5 to 7. As a result, the selection signal as an output of the gate circuits G1 and G2 has a waveform corresponding to only the even cycle of the internal clock signal.
Therefore, the duty detection circuit shown in FIG. 11 can detect a duty by extracting only the duty in the even cycle (or the odd cycle). Consequently, by providing the duty detection circuit for the even cycle and the duty detection circuit for the odd cycle, these duty detection circuits can be applied to the two-phase DLL circuit.
Further, because the output of the gate circuit G2 can be supplied to the discharge transistor TR2 after being delayed by the delay circuit D1, a period during which both transistors are turned off are inserted into between the on period of the discharge transistor TR1 and the on period of the discharge transistor TR2. Consequently, when the discharge transistors TR1 and TR2 change from off to on, the potential of the discharge node BIASND is precharged to about a ground potential, and there arises no difference in discharge speeds.
However, because the charge transistors TR3 and TR4 are omitted in the duty detection circuit shown in FIG. 11, the potential difference ΔV appearing in the detection lines LDUTYHB and LDUTYLB is smaller than that in the duty detection circuit shown in FIG. 9. This problem is considered to be solved by adding the charge transistors TR3 and TR4 to the duty detection circuit shown in FIG. 11. However, when only the charge transistors TR3 and TR4 are added, other problems occur such as a variation between the control at the charge side and the control at the discharge side, and a variation between the control at the detection line LDUTYHB side and the control at the detection line LDUTYLB side.